Memory devices are well known in the art and used in, among other things, virtually all microprocessor and digital signal processor applications. One type of memory favored for many applications is Static Random Access Memory (SRAM). SRAM devices are fast and easy to use relative to many other types of memory devices. In addition, SRAM devices using metal-oxide-semiconductor (MOS) technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These attributes make SRAM devices particularly desirable for battery-powered equipment, such as laptop computers and personal digital assistants.
A high static noise margin (SNM) and write trip voltage (so-called “Vtrip”) are desired cell characteristics of a SRAM device. A high SNM is desired for circuit stability. If SNM is too low, READ operations may be disrupted. A high Vtrip is desired for adequate data write speed. If Vtrip is too low, WRITE operations may be disrupted. Unfortunately, the requirements for acceptable SNM and Vtrip limit the tolerances for acceptable SRAM yield during manufacturing, because increasing one typically decreases the other, as described below.
A typical six-transistor SRAM memory cell (the basic unit of a SRAM device) consists of two p-channel “pull-up” transistors, two n-channel “pull-down” transistors and two access transistors, which are typically n-channel transistors. The strength of the p-doped and n-doped channels of the transistors affects the performance of the SRAM memory cell as a whole.
For example, a strong n-channel can cause SNM to be unsuitably low, particularly when accompanied by a weak p-channel. One might be tempted to weaken the n-channel and/or strengthen the p-channel to achieve a satisfactory SNM. However, a weak n-channel can cause Vtrip to be unsuitably low, particularly when accompanied by a strong p-channel.
Thus, existing SRAM devices are challenged by the competing and contradicting objectives of providing a weak n-channel (and/or a strong p-channel) to achieve an acceptable SNM and providing a strong n-channel (and/or a weak p-channel) to achieve an acceptable Vtrip. Moreover, this trade-off between SNM and Vtrip (and, thus, between reliable READ and WRITE operations) becomes increasingly constrained with continued miniaturization and lower operating voltages, since these amplify the effect of normal manufacturing variations. The result is that manufacturing yield has been diminishing, raising the cost of the devices that are successfully manufactured.
Accordingly, what is needed in the art is an SRAM device having improved worst-case SNM and Vtrip over a range of transistor characteristics. What is further needed in the art is a way to increase SRAM yield.